Method for fabricating semiconductor device

ABSTRACT

A method for fabricating a semiconductor device is provided, the method including forming a SiGe epitaxial layer pattern and a first Si epitaxial layer pattern on a semiconductor substrate, forming a second Si epitaxial layer on the entire surface, etching the second Si epitaxial layer and a predetermined thickness of the semiconductor substrate to form a trench defining an active region, removing the SiGe epitaxial layer pattern through a sidewall of the trench to form a space under the first Si epitaxial layer, forming a gap-filling insulating film to at least fill up the space and the trench, forming a gate oxide film on the second Si epitaxial layer, and depositing and patterning a gate conductive layer and a hard mask layer on the entire surface to form a gate in the gate region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a method for fabricating asemiconductor device, and more specifically to a method for fabricatinga semiconductor device wherein a gate is formed on a stepped Siepitaxial layer in order to increase an effective length of a gatechannel, and an oxide film is only formed at the interface of the Siepitaxial layer under a bit line contact and the semiconductorsubstrate, thereby improving a characteristic of a leakage current for astorage node junction.

2. Description of the Related Art

FIG. 1 is a layout illustrating a conventional method for fabricating asemiconductor device, wherein reference numerals 1000 a, 1, 2 and 3denote a cell region, an active region, a first gate region and a secondgate region, respectively.

FIGS. 2 a through 2 f are cross-sectional views illustrating aconventional method for fabricating a semiconductor device, whereinFIGS. 2 a(i) through 2 f(i) are cross-sectional views taken along theline I-I′ in FIG. 1, and FIGS. 2 a(ii) through 2 f(ii) arecross-sectional views in a core/peripheral circuit region 1000 b.

Referring to FIG. 2 a, a stacked structure of a SiGe epitaxial layer(not shown), a first Si epitaxial layer (not shown), a first oxide film(not shown) and a first nitride film (not shown) is formed on asemiconductor substrate 10 having a cell region 1000 a and acore/peripheral circuit region 1000 b defined therein.

Next, a first photoresist film (not shown) is deposited on the entiresurface of the first nitride film (not shown) in the cell region 1000 aand the core/peripheral circuit region 1000 b.

Thereafter, the first photoresist film (not shown) is exposed anddeveloped to form a first photoresist film pattern (not shown) exposingthe first gate region 2 of FIG. 1 and cover the entire core/peripheralcircuit region 1000 b.

After that, the stacked structure is etched using the first photoresistfilm pattern as an etching mask to expose the semiconductor substrate 10of the first gate region 2 and the entire core/peripheral circuit region1000 b.

The first photoresist film pattern is then removed.

Referring FIG. 2 b, a first nitride film pattern 19 and a first oxidefilm pattern 17 in the cell region 1000 a are removed via a wet etchingmethod.

Next, a second Si expitaxial layer 25 is formed on the entire surface ofthe cell region 1000 a and the core/peripheral circuit region 1000 b.

Referring to FIG. 2 c, a second oxide film 30 and a second nitride film35 are formed on the second Si epitaxial layer 25 in the cell region1000 a and the core/peripheral circuit region 1000 b.

Next, a second photoresist film (not shown) is deposited on the entiresurface of the second nitride film 35. The second photoresist film isthen exposed and developed to form a second photoresist film pattern(not shown) defining the active region 1 of FIG. 1 in the cell region1000 a, and also an active region in the core/peripheral circuit region1000 b.

Thereafter, the second nitride film 35, the second oxide film 30, thesecond Si epitaxial layer 25, the first Si epitaxial layer pattern 15,the SiGe epitaxial layer pattern 13 and a predetermined thickness of thesemiconductor substrate 10 are etched using the second photoresist filmpattern as an etching mask to form a trench 40 in the cell region 1000 aand the core/peripheral circuit region 1000 b.

After that, the second photoresist film pattern (not shown) is removed.The SiGe epitaxial layer pattern 13 is then etched through a sidewall ofthe trench 40 via a wet etching method to form a space 27 under thefirst Si epitaxial layer pattern 15.

Referring to FIG. 2 d, a gap-filling insulating film 45 is formed on theentire surface to fill up the space 27 and the trench 40 in the cellregion 1000 a and to fill up the trench 40 in the core/peripheralcircuit region 1000 b.

Next, the gap-filling insulating film 45 is polished until the secondnitride film 35 is exposed. The gap-filling insulating film 45 serves asa device isolation film.

Thereafter, a predetermined thickness of the gap-filling insulating film45 in the trench 40 is etched. The second nitride film 35 is thenremoved via a wet etching method.

After that, a well implant process and a channel implant process areperformed so as to adjust impurity concentrations in the cell region1000 a and the core/peripheral circuit region 1000 b.

Referring to FIG. 2 e, the second oxide film 30 in the cell region 1000a and the core/peripheral circuit region 1000 b is removed via a wetetching method to expose the second Si epitaxial layer 25. A gate oxidefilm 50 is then formed on the exposed second Si epitaxial layer 25.

Next, gate conductive layers 60 and 70, and a hard mask insulating film80 are formed on the gate oxide film 50 and the gap-filling insulatingfilm 45 in the cell region 1000 a and the core/peripheral circuit region1000 b.

Referring to FIG. 2 f, a third photoresist film (not shown) is depositedon the hard mask insulating film 80 in the cell region 1000 a and thecore/peripheral circuit region 1000 b.

Thereafter, the third photoresist film (not shown) is exposed anddeveloped to form a third photoresist film pattern defining the secondgate region 3 of FIG. 1 and a gate region (not shown) in thecore/peripheral circuit region 1000 b. Specifically, the thirdphotoresist film pattern exposes a bit line contact region and storagenode contact regions in the cell region 1000 a and covers a region wherea gate is to be formed in the core/peripheral circuit region 1000 b.

Next, the hard mask insulating film 80 and the gate conductive layers 70and 60 are etched using the third photoresist film pattern as an etchingmask to respectively form a gate 90 in the cell region 1000 a and thecore/peripheral circuit region 1000 b.

However, in accordance with the above-described conventional method, thegate 90 of the active region is formed on a plane second Si epitaxiallayer. As a result, a gate channel length is decreased as a design ruleof the semiconductor device is reduced.

Moreover, an oxide film is formed at the interface of the Si epitaxiallayer under a storage node contact and the semiconductor substrate.Accordingly, the leakage current for a storage node junction is highlydepended upon an interface characteristic between the Si epitaxial layerand an oxide film.

In addition, the SiGe epitaxial layer under the storage node contact isremoved for forming a device isolation film. As a result, Ge in the SiGeepitaxial layer is diffused into the first Si epitaxial layer, thesecond Si epitaxial layer and the semiconductor substrate due to heattreatment processes prior to the formation of the device isolation film.Accordingly, there is a problem such as increase in the leakage currentfor the storage node junction.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a method forfabricating a semiconductor device wherein a gate is formed on a steppedSi epitaxial layer to increase an effective length of a gate channel,and an oxide film is only formed at the interface of the Si epitaxiallayer under a bit line contact and the semiconductor substrate, therebyimproving a characteristic of a leakage current for a storage nodejunction.

In order to achieve the object of the present invention, there isprovided a method for fabricating a semiconductor device comprising thesteps:

(a) forming a SiGe epitaxial layer, a first Si epitaxial layer and aninsulating film on a semiconductor substrate, (b) etching apredetermined region of the insulating film, the first Si epitaxiallayer and the SiGe epitaxial layer to expose the semiconductorsubstrate, wherein the predetermined region includes a storage nodecontact region and a portion of a gate region adjacent thereto, (c)removing the insulating film, (d) forming a second Si epitaxial layer onthe entire surface including the exposed semiconductor substrate, (e)etching the second Si epitaxial layer, the first Si epitaxial layer, theSiGe epitaxial layer and a predetermined thickness of the semiconductorsubstrate to form a trench defining an active region, (f) removing theSiGe epitaxial layer through a sidewall of the trench to form a spaceunder the first Si epitaxial layer, (g) forming a gap-filling insulatingfilm to at least fill up the space and the trench, (h) forming a gateoxide film on the second Si epitaxial layer, and (i) depositing andpatterning a gate conductive layer and a hard mask layer on the entiresurface to form a gate in the gate region.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a layout illustrating a conventional method for fabricating asemiconductor device.

FIGS. 2 a through 2 f are cross-sectional views illustrating aconventional method for fabricating a semiconductor device.

FIG. 3 is a layout illustrating a method for fabricating a semiconductordevice in accordance with a preferred embodiment of the presentinvention.

FIGS. 4 a through 4 f and FIG. 5 are cross-sectional views illustratinga method for fabricating a semiconductor device according to a preferredembodiment of the present invention.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

Reference will now be made in detail to exemplary embodiments of thepresent invention. Wherever possible, the same reference numbers will beused throughout the drawings to refer to the same or like parts.

FIG. 3 is a layout illustrating a method for fabricating a semiconductordevice in accordance with a preferred embodiment of the presentinvention, wherein reference numerals 2000 a, 101, 102 and 103 denote acell region, an active region, a contact region and a gate region,respectively.

FIGS. 4 a through 4 f illustrate a method for fabricating asemiconductor device according to a preferred embodiment of the presentinvention, wherein FIGS. 4 a(i) through 4 f(i) are cross-sectional viewstaken along the line II-II′ of FIG. 3, and FIGS. 4 a(ii) through 4 f(ii)are cross-sectional views in a core/peripheral circuit region 2000 b.

Referring to FIG. 4 a, a stacked structure of a SiGe epitaxial layer(not shown), a first Si epitaxial layer (not shown) and an insulatingfilm (not shown) is formed on a semiconductor substrate 110 having acell region 2000 a and a core/peripheral circuit region 2000 b definedtherein. Preferably, the insulating film comprises an oxide film or astacked structure of an oxide film and a nitride film.

Next, a first photoresist film (not shown) is deposited on the entiresurface of the insulating film in the cell region 2000 a and thecore/peripheral circuit region 2000 b.

Thereafter, the first photoresist film (not shown) is exposed anddeveloped to form a first photoresist film pattern (not shown) exposingthe contact region 102 of FIG. 3 and cover the entire core/peripheralcircuit region 2000 b. The contact region 102 includes a storage nodecontact region and a portion of the gate region 103 adjacent thereto.Preferably, the portion of the gate region 103 has a line width of Mranging from ⅓F to F, where F is a gate line width.

After that, the stacked structure is etched using the first photoresistfilm pattern as an etching mask to expose the semiconductor substrate110 of the contact region 102 and the entire core/peripheral circuitregion 2000 b.

The first photoresist film pattern is then removed.

Referring to FIG. 4 b, an insulating film pattern 120 in the cell region2000 a is removed. Preferably, the removal process for the insulatingfilm pattern 120 is performed via a wet etching method.

Next, a second Si epitaxial layer 125 is formed on the entire surface ofthe cell region 2000 a and the core/peripheral circuit region 2000 b.Preferably, a thickness of the second Si epitaxial layer 125 ranges from10 nm to 100 nm.

The second epitaxial layer 125 in the cell region 2000 a may have a stepdifference due to the first Si epitaxial layer pattern 115 and the SiGeepitaxial layer pattern 113.

Referring to FIG. 4 c, a second oxide film 130 and a second nitride film135 are formed on the second Si epitaxial layer 125 in the cell region2000 a and the core/peripheral circuit region 2000 b.

Next, a second photoresist film (not shown) is deposited on the entiresurface of the second nitride film 135. The photoresist film is thenexposed and developed to form a second photoresist film pattern (notshown) defining the active region 101 of FIG. 3 in the cell region 2000a and also an active region in the core/peripheral circuit region 2000b.

Thereafter, the second nitride film 135, the second oxide film 130, thesecond Si epitaxial layer 125, the first Si epitaxial layer pattern 115,the SiGe epitaxial layer pattern 113 and a predetermined thickness ofthe semiconductor substrate 110 are etched using the second photoresistfilm pattern as an etching mask to form a trench 140 in the cell region2000 a and the core/peripheral circuit region 2000 b.

After that, the second photoresist film pattern (not shown) is removed.The SiGe epitaxial layer pattern 113 is then etched through a sidewallof the trench 140 to form a space 127 under the first Si epitaxial layerpattern 115.

FIG. 5 is a cross-sectional view taken along the line III-III′ of FIG. 3illustrating the structure of FIG. 4 c(i) including the space 127 havinga undercut structure.

Preferably, the removal process for the SiGe epitaxial layer pattern 113is preformed via a wet etching method utilizing a mixed etchantcontaining HF, H₂O₂ and CH₃CHOOH, a plasma etching method utilizing amixed gas containing (CF₃ or CH₂F₂), N₂ and O₂, or combinations thereof.Moreover, a volume ratio of HF, H₂O₂ and CH₃COOH in the mixed etchant ispreferably 1:2:3.

Referring to FIG. 4 d, a gap-filling insulating film 145 is formed onthe entire surface to at least fill up the space 127 and the trench 140in the cell region 2000 a and to fill up the trench 140 in thecore/peripheral circuit region 2000 b.

Preferably, the formation process of the gap-filling insulating film 145may include forming a thermal oxide film filling up the space 127 andforming an oxide film for a device isolation film filling up the trench140. A nitride film may be further formed at an interface of the thermaloxide film and the oxide film for the device isolation film.

Moreover, the formation process of the gap-filling insulating film 145may include forming a thermal oxide film to fill up a portion of thespace 127, forming a nitride film to fill up the remaining portion ofthe space 127, and forming an oxide film for the device isolation filmto fill up the trench 140.

Next, the gap-filling insulating film 145 is polished until the secondnitride film 135 is exposed. The gap-filling insulating film 145 in thetrench 140 serves as a device isolation film.

Thereafter, a predetermined thickness of the gap-filling insulating film145 in the trench 140 is etched. The second nitride film 135 is thenremoved. Preferably, the etching process for the gap-fill insulatingfilm 145 is performed via a wet etching method. The removal process forthe second nitride film 135 is preferably preformed via a wet etchingmethod.

After that, well implant processes and channel implant processes areperformed so as to respectively adjust impurity concentrations in thecell region 2000 a and the core/peripheral circuit region 2000 b.

Referring to FIG. 4 e, the second oxide film 130 in the cell region 2000a and the core/peripheral circuit region 2000 b is removed to expose thesecond Si epitaxial layer 125. A gate oxide film 150 is then formed onthe exposed second Si epitaxial layer 125. Preferably, the removalprocess for the second oxide film 130 is performed via a wet etchingmethod.

Next, a stacked structure of a gate conductive layer 175 and a hard masklayer 180 is formed on the gate oxide film 150 and the gap-fillinginsulating film 145 in the cell region 2000 a and the core/peripheralcircuit region 2000 b. Preferably, the gate conductive layer 175comprises a lower conductive layer 160 and an upper conductive layer170.

Referring to FIG. 4 f, a third photoresist film (not shown) is depositedon the hard mask layer 180 in the cell region 2000 a and thecore/peripheral circuit region 2000 b.

Thereafter, the third photoresist film (not shown) is exposed anddeveloped to form a third photoresist film pattern defining the gateregion 103 of FIG. 3 and a gate region (not shown) in thecore/peripheral circuit region 2000 b. Specifically, the thirdphotoresist film pattern exposes a bit line contact region and storagenode contact regions in the cell region 2000 a and covers a region wherea gate is to be formed in the core/peripheral circuit region 2000 b.

Next, the stacked structure is patterned using the third photoresistfilm pattern as an etching mask to respectively form a gate 190 in thecell region 2000 a and the core/peripheral circuit region 2000 b.

In addition, subsequent processes such as an ion-implant process forforming source/drain regions in the active regions, a process forforming a spacer on a sidewall of the gate 190, a process for forming alanding plug, a process for forming a bit line contact and a bit line, aprocess for forming a capacitor and a process for forming aninterconnect may be done.

As described above, the method for fabricating a semiconductor device inaccordance with the present invention provides exposing the contactregion including the storage node contact region and a portion of thegate region adjacent thereto and only forming an oxide film at theinterface of the Si epitaxial layer under both a bit line contact andthe semiconductor substrate. Accordingly, capacitance for a bit linecontact and a short-channel effect of a cell transistor are improved.

As shown in FIG. 4 f, the gate 190 in the cell region 2000 a is formedon a structure having a step difference instead of over a planestructure to increase an effective length of the gate channel, and thestorage node contact is formed on the Si epitaxial layer without theoxide film to minimize the leakage current of the storage node junction.Accordingly, a refresh characteristic of a DRAM can be improved.

The foregoing description of various embodiments of the invention hasbeen presented for purposes of illustration and description. It is notintended to be exhaustive or to limit the invention to the precise formdisclosed, and modifications and variations are possible in light of theabove teachings or may be acquired from practice of the invention. Theembodiments were chosen and described in order to explain the principlesof the invention and its practical application to enable one skilled inthe art to utilize the invention in various embodiments and with variousmodifications as are suited to the particular use contemplated.

1. A method for fabricating a semiconductor device, comprising the stepsof: (a) forming a SiGe epitaxial layer, a first Si epitaxial layer andan insulating film on a semiconductor substrate; (b) etching apredetermined region of the insulating film, the first Si epitaxiallayer and the SiGe epitaxial layer to expose the semiconductorsubstrate, wherein the predetermined region includes a storage nodecontact region and a portion of a gate region adjacent thereto; (c)removing the insulating film; (d) forming a second Si epitaxial layer onthe entire surface including the exposed semiconductor substrate; (e)etching the second Si epitaxial layer, the first Si epitaxial layer, theSiGe epitaxial layer and a predetermined thickness of the semiconductorsubstrate to form a trench defining an active region; (f) removing theSiGe epitaxial layer through a sidewall of the trench to form a spaceunder the first Si epitaxial layer; (g) forming a gap-filling insulatingfilm to at least fill up the space and the trench; (h) forming a gateoxide film on the second Si epitaxial layer; and (i) depositing andpatterning a gate conductive layer and a hard mask layer on the entiresurface to form a gate in the gate region.
 2. The method according toclaim 1, wherein the step (b) comprises: forming a photoresist film onthe entire surface of the semiconductor substrate; forming a photoresistfilm pattern exposing the predetermined region by exposing anddeveloping the photoresist film, wherein the portion of the gate regionof the predetermined region has a line width of M; and etching theinsulating film, the Si epitaxial layer and the SiGe epitaxial layerusing the photoresist film pattern as an etching mask.
 3. The methodaccording to claim 2, wherein the M ranges from ⅓F to F, wherein F is agate line width.
 4. The method according to claim 1, wherein theinsulating film comprises an oxide film.
 5. The method according toclaim 1, wherein the insulating film comprises a stacked structure of anoxide film and a nitride film.
 6. The method according to claim 1,wherein the removal process for the insulating film in the step (e) isperformed via a wet etching method.
 7. The method according to claim 1,wherein a thickness of the second Si epitaxial layer ranges from 10 to100 nm.
 8. The method according to claim 1, wherein the removal processfor the SiGe epitaxial layer in the step (f) is performed via one methodselected from the group consisting of a wet etching method utilizing amixed etchant containing HF, H₂O₂ and CH₃COOH, a plasma etching methodutilizing a mixed gas containing (CF₄ or CH₂F₂), N₂ and O₂, andcombinations thereof.
 9. The method according to claim 8, wherein avolume ratio of HF, H₂O₂ and CH₃COOH in the mixed etchant is 1:2:3. 10.The method according to claim 1, wherein the step (g) comprises: forminga thermal oxide film filling up the space; and forming an oxide film fora device isolation film to fill up the trench.
 11. The method accordingto claim 10, further comprising forming a nitride film at the interfaceof the thermal oxide film and the oxide film for the device isolationfilm.
 12. The method according to claim 1, wherein the step (g)comprises: forming a thermal oxide film to fill a portion of the space;forming a nitride film to fill up a remaining portion of the space; andforming an oxide film for the device isolation film to fill up thetrench.